Semiconductor devices may be required to operate at high speeds with large information processing capabilities. Semiconductor devices may also be required to have large storage capacities. To satisfy such requirements, semiconductor manufacturing technology has improved. For example, semiconductor devices may be faster, more highly integrated, and more reliable.
To increase a level of integration, semiconductor devices may be manufactured by forming a metal interconnection in each layer with a multi-layered structure, or by narrowing an interval between metal interconnections in a given layer.
However, as the interval between metal interconnections becomes narrower, it may be important to reduce parasitic resistance or capacitance formed either between metal interconnections adjacent to each other on the same layer or between metal interconnection in adjacent layers (i.e. above and below).
In very highly integrated semiconductor devices, parasitic resistance and capacitance components formed in a multi-layered metal interconnection structure may degrade electrical characteristics of the semiconductor devices. This may be due to a delay induced by resistance capacitance (RC delay), which may increase a power consumption of semiconductor devices.
Therefore, it may be important to develop a technology for multi-layered metal interconnections having a low RC value in very highly integrated semiconductor devices.
To form a high-performance multi-layered metal interconnections having a low RC value, an interconnection layer may be formed by using a metal having low specific resistance. Alternatively, an insulating layer, for example having a low dielectric constant, may be used.
To reduce capacitance, a material having a low dielectric constant may be used.
In the related art, FSG (Fluorine Silicate Glass) layers having a dielectric constant lower than USG (Undoped Silicate Glass) have been used as interlayer dielectric layers. In such devices, however, the dielectric constant of the FSG layers may be reduced by increasing a density of fluorine. It may be difficult to control properties of the FSG layers in such instances. That is, there may be limitations as to how much the capacitance can be reduced by using only an FSG layer.